By Steve Leibson

Microprocessor cores used for SOC layout are the direct descendents of Intel’s unique 4004 microprocessor. simply as packaged microprocessor ICs range broadly of their attributes, so do microprocessors packaged as IP cores. despite the fact that, SOC designers nonetheless evaluate and choose processor cores the way in which they formerly in comparison and chosen packaged microprocessor ICs. the large challenge with this option strategy is that it assumes that the legislation of the microprocessor universe have remained unchanged for many years. This assumption is not any longer valid.

Processor cores for SOC designs may be way more plastic than microprocessor ICs for board-level method designs. Shaping those cores for particular purposes produces far better processor potency and masses reduce procedure clock premiums. jointly, Tensilica’s Xtensa and Diamond processor cores represent a family members of software-compatible microprocessors masking a really vast functionality variety from basic keep watch over processors, to DSPs, to 3-way superscalar processors. but all of those processors use an analogous software-development instruments in order that programmers accustomed to one processor within the relations can simply change to another.

This publication emphasizes a processor-centric MPSOC (multiple-processor SOC) layout kind formed via the realities of the 21st-century and nanometer silicon. It advocates the project of projects to firmware-controlled processors every time attainable to maximise SOC flexibility, minimize energy dissipation, decrease the scale and variety of hand-built common sense blocks, scale back the linked verification attempt, and reduce the general layout risk.

· a necessary, no-nonsense consultant to the layout of 21st-century mega-gate SOCs utilizing nanometer silicon.
· Discusses latest key concerns affecting SOC layout, in response to author's many years of private event in constructing huge electronic structures as a layout engineer whereas operating at Hewlett-Packard's computing device laptop department and at EDA computing device pioneer Cadnetix, and protecting such issues as an award-winning expertise journalist and editor-in-chief for EDN journal and the Microprocessor Report.
· Explores conventionally accredited limitations and perceived limits of processor-based procedure layout after which explodes those man made constraints via a clean outlook on and dialogue of the detailed talents of processor cores designed in particular for SOC design.
· Thorough exploration of the evolution of processors and processor cores used for ASIC and SOC layout with a glance at the place the has come from, and the place it truly is going.
· Easy-to-understand causes of the functions of configurable and extensible processor cores via an in depth exam of Tensilica's configurable, extensible Xtensa processor center and 6 pre-configured Diamond cores.
· the main accomplished review on hand of the sensible facets of configuring and utilizing a number of processor cores to accomplish very tough and bold SOC fee, functionality, and tool layout goals.

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Designing SOCs with Configured Cores: Unleashing the Tensilica Xtensa and Diamond Cores (Systems on Silicon) by Steve Leibson

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